? ? high? speed? cmos ? logic? ? ? 54HC04 ? ? ? ? hex inverter gate logic ic in bare die form ? output drive capability: 10 lsttl loads ? low input current: 1a ? outputs directly inter face cmos, nmos and ttl rev 1.0 22/04/19 features: ? ? operating voltage range: 2v to 6v ? function compatible with 54ls04 ? ? high noise immunity cmos process ? ? full military temperature range. ? ? ? ? ordering information the following part suffixes apply: ? no suffix - mil-std-883 /2010b visual inspection the 54 hc04 hex inverter gate is fabricated on a .35m advanced cmos process combining high speed lsttl performance with cmos low p ower. the device contains six independent inverters wit h standard push-pull outputs which perform the boolean func tion y = ? in positive logic. internal circuitry comprises of three stages and includes buffered output for high noise i mmunity and stability. inputs are compatible with standa rd cmos outputs; with pull-up resistors, they are compatib le with lsttl outputs. the product die size is significant ly smaller than industry peers due to its re-design and production using a more advanced cmos process. description die dimensions in m (mils) 560 (22) ? ? ? ? ? ? ? ? ? ? ? ? die size (unsawn) 560 x 750 22 x 30 m mils minimum bond pad size 90 x 90 3.54 x 3.54 m mils die thickness 350 (20) 13.78 (0.79) m mils ? h - mil-std-883 /2010b visual inspection + mil-prf-38534 class h lat ? k - mil-std-883 /2010a visual inspection (space) + mil-prf-38534 class k lat lat = lot acceptance test. for further information on la t process flows see below. www.siliconsupplies. com\quality\bare-die-lot-qualification supply formats: mechanical specification ? default C die in waffle pack (400 per tray capacity) ? sawn wafer on tape C on request ? unsawn wafer C on request 750 (30) ? die thickness <> 350m(14 mils) C on request top metal composition al 1%si 1.1m ? assembled into ceramic package C on request back metal composition n/a C bare si page ? 1 ? of ? 5 ? www.siliconsupplies.com a l l d a t a s h e e t . c o m
page ? 2 ? of ? 5 ? www.siliconsupplies.com ? d? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? high? speed? cmos ? logic? ? ? 54HC04 rev 1.0 22/04/19 pad layout and functions pad 14 = v cc pad 7 = gnd ? logic diagram truth table inputs a outp ut y h l l h h = high level (steady state) l ? = ? low ? level? (steady ? state) ? 4 5 3 2 1 14 13 12 11 10 9 8 7 6 die id 750m (30 mils) coordinates (m) pad function x y 1 1a 210 155 2 1y 210 320 3 2a 60 320 4 2y -103 320 5 3a -210 320 6 3y -210 117 7 gnd -210 0 8 4y -210 -117 9 4a -210 -320 10 5y -103 -320 11 5a 60 -320 12 6y 210 -320 13 6a 210 -178 14 v cc 210 9 connect chip back to v cc or float 0,0 560m (22 mils) a l l d a t a s h e e t . c o m
page ? 3 ? of ? 5 ? www.siliconsupplies.com ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? high? speed? cmos ? logic? ? ? 54HC04 rev 1.0 22/04/19 parameter symbol min max units supply voltage v cc 2 6 v dc input or output voltage v in ,v out 0 v cc v operating temperature range t j -55 +125 c v cc = 2v 0 1000 v cc = 4.5v 0 500 input rise or fall times t r , t f v cc = 6.0v 0 400 ns ? recommended operating conditions 3 (voltages referenced to gnd) absolute maximum ratings 1 parameter symbol value unit dc supply voltage (referenced to gnd) v cc -0.5 to +7.0 v dc input voltage (referenced to gnd) v in -0.5 to v cc +0.5 v dc output voltage (referenced to gnd) v out -0.5 to v cc +0.5 v dc input current i in 20 ma dc output current, per pad i out 25 ma dc supply current, v cc or gnd i cc 50 ma power dissipation in still air 2 p d 750 mw storage temperature range t stg -65 to 150 c 3. ? this device contains protecti on circuitry to guard against dama ge due to high static voltages or electric fields. however, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either gnd or v cc ). unused outputs must be left open. dc electrical characteristics (voltages referenced to gnd) 1. ? operation above the absolute maxi mum rating may cause device fa ilure. operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. measured in plastic dip package , results in die form are depen dent on die attach and assembly method. limits parameter symbol v cc conditions 25c 85c full range 4 units 2.0v 1.5 1.5 1.5 3.0v 2.1 2.1 2.1 4.5v 3.15 3.15 3.15 minimum high-level input voltage v ih 6.0v v out = 0.1v or v cc -0.1v i out 20a 4.2 4.2 4.2 v 2.0v 0.5 0.5 0.5 3.0v 0.9 0.9 0.9 4.5v 1.35 1.35 1.35 maximum low-level input voltage v il 6.0v v out = 0.1v or v cc -0.1v i out 20a 1.8 1.8 1.8 v 4. -55?c t j +125?c a l l d a t a s h e e t . c o m
? ? high? speed? cmos ? logic? ? ? 54HC04 ? dc electrical characteristics continued (voltages referenced to gnd) r ev 1.0 22/04/19 ? limits parameter ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 5. not production tested in die fo rm, characterized by chip desi gn and tested in package. a c electrical characteristics 5 symbol v cc conditions full range 4 units 25c 85c 2.0v 1.9 1.9 1.9 4.5v 4.4 4.4 4.4 v in = v ih or v il v i out 20a 6.0v 5.9 5.9 5.9 3.0v v in = v ih or v il i out 2.4ma 2.48 2.34 2.20 4.5v v in = v ih or v il i out 4.0ma 3.98 3.84 3.70 minimum high-level output voltage v oh 6.0v v in = v ih or v il i out 5.2ma 5.48 5.34 5.20 v 2.0v 0.1 0.1 0.1 4.5v 0.1 0.1 0.1 v in = v il or v il i out 20a 6.0v 0.1 0.1 0.1 v 3.0v v in = v il or v il i out 2.4ma 0.26 0.33 0.40 4.5v v in = v il or v il i out 4.0ma 0.26 0.33 0.40 maximum low-level output voltage v ol 6.0v v in = v il or v il i out 5.2ma 0.26 0.33 0.40 v maximum input leakage current i in 6.0v v in = v cc or gnd 0.1 1.0 1.0 a maximum quiescent supply leakage current i cc 6.0v v in = v cc or gnd i out = 0a 1 10 40 a limits parameter symbol v cc conditions 25c 85c full range 4 units 2.0v 75 95 110 3.0v 30 40 55 4.5v 15 19 22 maximum propagation delay, input a or b to output y (figure 1,2) t plh, t phl c l = 50pf, t r = t f = 6ns ns 6.0v 13 16 19 2.0v 75 95 110 3.0v 27 32 36 4.5v 15 19 22 maximum output rise and fall time, c l = 50pf, any output (figure 1,2) t tlh, t thl ns t r = t f = 6ns 6.0v 13 16 19 page ? 4 ? of ? 5 ? www.siliconsupplies.com a l l d a t a s h e e t . c o m
page ? 5 ? of ? 5 ? www.siliconsupplies.com ? ? high? speed? cmos ? logic? ? ? 54HC04 rev 1.0 22/04/19 ? ? ? ? ? ? a c electrical characteristics continued 5 6. used to determine the no-load dynamic power consumption: p d = c pd v cc limits parameter ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? disclaimer: the information given in this document shall in no event be reg arded as a guarantee of conditions or characteristics. with re spect to any examples or hints given herei n, any typical values stated h erein and/or any information r egarding the application of the d evice, silicon supplies ltd hereby disclaims any and all warranties and liabilities of any kind. life support policy : silicon supplies ltd components may be used in life support dev ices or systems only with the express written approval of silicon supplies ltd, if a failure of such componen ts can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted i n the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. switchin g waveform dut c l * ? ? output test point test circuit * includes all probe and jig capacitance figure 1 C propagation ? delay ? & ? output ? transition ? time figure 2 2 f + i cc v cc . symbol v cc conditions units full range 4 25c 85c maximum input capacitance c in - - 10 10 10 pf typical power dissipation t a = 25c, pf capacitance per gate 6 c pd - v cc =5.0v 20 ? a l l d a t a s h e e t . c o m
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